1. Field of the Invention
The present invention relates to a test apparatus for semiconductor device, and in particular to an arrangement for test of the package of a semiconductor device such as a flip-chip package or a fine-pitch ball grid array (FP-BGA).
2. Description of the Related Art
In recent years, for the high integration and large capacity of an IC chip, especially for LSI and VLSI chips, packages for mounting a semiconductor chip are reduced in size and have a great number of pins, and the spacing between leads on the lead frame has become narrower and narrower. In the case where such a semiconductor chip is packaged, there are adopted a flip-chip package and BGA (ball grid array) which are a surface-mount package where the semiconductor chip is sealed with resin on a substrate having an array of solder balls.
A conventional test method for such a semiconductor device having an array of solder bumps thereon has been proposed in Japanese Patent Unexamined Publication No. 5-267393. This test method uses an interposer which is comprised of an insulating plate having the electrodes through the insulating plate. A semiconductor device to be tested is placed on the interposer with aligning the respective solder bumps of the device with the electrodes of the interposer. Subsequently, they are heated and thereby the solder bumps are melted and connected to the electrodes of the interposer. The interposer mounted with the semiconductor device is placed on a test substrate and is pressed so that the electrodes of the interposer are electrically connected to the terminal electrodes of the test substrate.
Another conventional test method has been proposed in Japanese Patent Unexamined Publication No. 6-82521. This test method uses an elastomeric conductive polymer interconnection (ECPI) layer and a spacer having openings to electrically connect the solder bumps of the device to the terminal electrodes of the test substrate through the openings and the conductive polymer chains.